Nanoimprint lithography: the new way to print chips beyond EUV

Almost every top chip in the world is printed with one kind of machine: an EUV scanner from the Dutch company ASML. Japan wants to offer other routes. Canon now sells a chip “printer” that works like a rubber stamp, Dai Nippon Printing has made stamps fine enough for future 1.4-nanometre chips, Nikon is building mask-free printers for chiplets, and a lab in Okinawa has sketched a much simpler EUV machine.

Why it matters: lithography, the step that “prints” circuit patterns onto silicon, is the most expensive part of making advanced chips. Cheaper or thriftier ways to do it could help more countries, labs and companies build modern chips, and cut the huge electricity bill of chip factories. None of these ideas has replaced EUV yet, so here is what is real, what is promised and what is still missing.

Key takeaways

EUV rules the top end: only ASML makes EUV machines, at about €170 million to €350 million each (press estimates).
Canon’s stamp is real: its FPA-1200NZ2C nanoimprint machine prints 14 nm lines (5 nm-class chips) and shipped to a US research consortium in Texas in 2024.
Finer stamps are coming: Dai Nippon Printing (DNP) showed a 10 nm template for 1.4 nm-generation chips and plans mass production in 2027.
Big energy claims: Canon and DNP say nanoimprint uses about a tenth of the power; OIST says its EUV design needs under 100 kW instead of over 1 MW (makers’ own figures).
New transistors too: 2 nm-class chips now wrap the gate all around the channel, and power wires are moving to the back of the chip.
Not in mass production yet: defects, layer alignment and stamp lifetime are still the hurdles, and memory chips are the most likely first users.

First, what is EUV, and why look beyond it?

Making a chip is a bit like making a photo print, over and over. A wafer (a thin disc of silicon) is coated with a resist, a light-sensitive layer like the coating on old camera film. Light shines through a mask, a stencil with the circuit drawing, and “draws” the pattern onto the resist. Repeat for dozens of layers and you get billions of transistors (the tiny on-off switches that do the computing).

The smaller the drawing, the shorter the light you need, just as a fine pencil draws thinner lines than a fat marker. EUV (extreme ultraviolet) light has a wavelength of only 13.5 nm, close to X-rays. To make it, a laser first flattens tiny falling drops of molten tin, then a second pulse turns each one into a glowing plasma, 50,000 times a second, ASML explains. Even air absorbs that light, so the whole trip happens in a vacuum and is steered by mirrors instead of lenses, ASML adds.

Six numbered steps inside a vacuum chamber: tin drops fall, a first laser pulse flattens each drop, a second pulse makes a plasma flash of EUV light, mirrors guide the light, a mask holds the chip pattern and the pattern lands on the wafer. Big numbers: 13.5 nm wavelength, 50,000 drops a second, 70 metres per second. — Inside an EUV machine: from a tin flash to the wafer, all in a vacuum (simplified) · Diagram: DIGITAL WOXTER TECHNEWS.

It works brilliantly, but it is a giant. Reuters put the newest High-NA EUV machine at about €350 million each, as ThePrint carried it, while standard EUV costs around €170 million, Tom’s Hardware reports. And only ASML sells them. That is the gap Japan’s engineers are aiming at.

An open, fully assembled ASML High-NA EUV machine in a white cleanroom: a wall of metal modules, tubes and blue cables as wide as a room. — An open, fully assembled ASML TWINSCAN EXE:5000, the first High-NA EUV machine · Image: ASML.

Why smaller chips need new transistors

Every chip starts as a wafer: a thin, mirror-polished slice cut from one huge crystal of almost perfectly pure silicon. Here is how sand becomes that slice.

Six numbered steps from quartz sand to a polished silicon wafer, with three big numbers: 99.999999999% purity, 300 mm wide and 0.775 mm thick — From sand to wafer: every chip starts as a slice of one giant silicon crystal · Illustration by DIGITAL WOXTER TECHNEWS.

All of this keeps alive an idea from 1965: Intel co-founder Gordon Moore’s observation that the number of transistors on a chip doubles roughly every two years, now known as Moore’s law (Wikipedia). The biggest chips went from 2,300 transistors in 1971 to 208 billion in NVIDIA’s B200 in 2024 (transistor count list, NVIDIA), and every big step needed a new invention.

Line chart of transistors per chip from 1971 to 2024 on a log scale, rising from 2,300 to 208 billion, with markers for ion implantation, CMP, copper wiring, high-k metal gate, FinFET, EUV and gate-all-around — Moore's law: each new invention kept the number of transistors per chip climbing · Illustration by DIGITAL WOXTER TECHNEWS.

First, a surprise: today’s “2 nm” or “3 nm” names are generation labels, not the size of any real part of the chip. They stopped matching a single measurement years ago, as IEEE Spectrum explains and an IEEE Spectrum proposal for a better yardstick also argues. What keeps shrinking is how many transistors fit in the same space.

Timeline of chip generations from 90 nm in 2003 to 2 nm in 2025, drawn as shrinking squares: planar transistors until 2012, FinFETs from 2012, gate-all-around from 2022, EUV in volume from 2019. Planned: TSMC A16 in 2026 and Rapidus 2 nm in 2027; High-NA EUV and nanoimprint aim at 2 nm and finer. — From 90 nm to 2 nm: today's "nm" names are generation labels, not real sizes · Diagram: DIGITAL WOXTER TECHNEWS.

To keep packing them in, the switch itself had to change. Picture a transistor as a tap on a garden hose: the gate squeezes the channel to stop or let current flow. Old “planar” transistors pressed on the channel from the top only. In 2011 Intel announced 3-D “tri-gate” transistors, better known as FinFETs, for its 22 nm chips, gripping a raised fin on three sides, as ScienceDaily and AnandTech reported.

The newest step is gate-all-around (GAA): the channel becomes a stack of thin sheets, and the gate wraps around every one, so less current leaks when the switch is off, IEEE Spectrum and Semiconductor Engineering explain. Samsung started making 3 nm GAA chips in June 2022, according to Samsung and AnandTech. TSMC’s N2, its first GAA process, entered volume production in the fourth quarter of 2025, Tom’s Hardware and TechSpot report, and Rapidus showed its first working 2 nm GAA prototypes in July 2025, as Rapidus and Tom’s Hardware reported.

Three 3D transistors side by side: planar with the red gate on top of a flat yellow channel, FinFET with the gate wrapped over two upright fins, and gate-all-around with the gate surrounding three stacked sheets — From planar to FinFET to gate-all-around: the gate grips the channel on more and more sides · Illustration by DIGITAL WOXTER TECHNEWS.

The other trick is backside power: moving the power wires underneath the transistors, a bit like putting a building’s water pipes in the basement so every floor has more room. Intel’s 18A, which it calls its first “2-nanometre class” node, combines GAA transistors (RibbonFET) with backside power (PowerVia) in its Panther Lake laptop chips, according to Intel and eeNews Europe. TSMC plans its own version, A16, for the second half of 2026, AnandTech and Semiconductor Engineering reported.

So who can actually make these newest chips? Only a handful of companies. Samsung started making its first 2 nm phone chip, the Exynos 2600, in 2025, TrendForce reported, joining TSMC and Intel. China’s SMIC, without EUV, has pushed its 7 nm-class process further but remains well short of real 5 nm, according to TechInsights, Tom’s Hardware and Mark LaPedus. Rapidus still targets the second half of its fiscal year 2027, but Bloomberg reported on 10 November 2026 that it is likely to miss that date after trouble making working 2 nm SRAM memory; Rapidus says it is on track, Electronics Weekly adds.

A table of chipmakers and chip generations: TSMC and Samsung make 10, 7, 5, 3 and 2 nm chips, with TSMC's A16 planned for 2026; Intel makes Intel 4, Intel 3 and 18A, a 1.8 nm-class process, since 2025; China's SMIC makes 7 nm-class chips without EUV; Japan's Rapidus plans 2 nm for 2027. — Who makes each chip generation today, and who plans to · Diagram: DIGITAL WOXTER TECHNEWS.

You probably carry one of these generations in your pocket. Here are some phones and laptops on sale and the chip generation inside each one (MacRumors, Android Authority, TechNode, Yole).

Phones and laptops grouped by chip generation: 2 nm (iPhone 18 Pro, Galaxy S26 in Europe, Panther Lake laptops), 3 nm (iPhone 17 Pro, Galaxy S26 Ultra, MacBook Pro M5) and 5 nm (iPhone 15, MacBook Air M2) — Which chip generation is inside some phones and laptops on sale · Illustration by DIGITAL WOXTER TECHNEWS.

Intel CEO Lip-Bu Tan holds up a shiny wafer covered in Panther Lake processor tiles made on Intel 18A. — A wafer of Panther Lake chips on Intel 18A, Intel's first "2 nm class" process · Image: Intel.

A silicon wafer from Rapidus carrying its first 2 nm gate-all-around prototype transistors. — Rapidus's first 2 nm gate-all-around prototype transistors on a silicon wafer (July 2025) · Image: Rapidus.

Nanoimprint: printing chips like a rubber stamp

Canon’s idea skips the light show. In nanoimprint lithography (NIL) a mask carved with the circuit pattern is pressed straight into the resist on the wafer, “like a stamp”, Canon says. Think of a waffle iron: the pattern is in the plate, and pressing it into the batter copies every square at once. Because no lenses or mirrors sit in between, the tiny features on the mask are copied faithfully.

Two rows of three steps. EUV: a laser hits tin drops that flash extreme ultraviolet light, mirrors bounce it off a patterned mask, and the light draws the pattern on a light-sensitive coating on the wafer. Nanoimprint: an inkjet places drops of liquid coating on the wafer, a stamp presses in while a flash of light hardens it, and the stamp lifts away leaving the pattern. — Two ways to print a chip: EUV draws the pattern with light, nanoimprint presses it in like a stamp (simplified) · Diagram: DIGITAL WOXTER TECHNEWS.

Canon launched its FPA-1200NZ2C in October 2023. It prints lines just 14 nm wide, which Canon says is equal to the 5 nm node (a “node” is a chip generation name rather than a ruler measurement). With better masks, Canon expects 10 nm lines, matching the 2 nm generation used in today’s most advanced phone and AI chips.

Four circles, each zooming far into the one before: a human hair 80,000 to 100,000 nanometres wide, Canon's 14 nanometre stamp lines, DNP's 10 nanometre template lines and a 2.5 nanometre strand of DNA. — How small is this? From a hair to a strand of DNA · Diagram: DIGITAL WOXTER TECHNEWS.

On 26 September 2024 Canon shipped one to the Texas Institute for Electronics, a consortium backed by the University of Texas at Austin, for research and prototype chips, according to Canon’s release and The Register. Canon’s CEO Fujio Mitarai has said its price will have “one digit less” than ASML’s EUV, as Tom’s Hardware reported from a Bloomberg interview, though no list price is public.

Canon's FPA-1200NZ2C nanoimprint lithography system, a large white cabinet-like machine for chip factories. — Canon's FPA-1200NZ2C, the nanoimprint machine shipped to Texas in 2024 · Image: Canon.

A stamp is only as good as its pattern, and that is where another Japanese giant comes in. In December 2025 Dai Nippon Printing (DNP) showed a nanoimprint template with 10 nm lines, aimed at 1.4 nm-generation logic chips. It got there with a trick called double patterning, which splits one dense drawing into two easier ones. DNP says the template can replace part of the EUV steps, uses about one-tenth of the exposure power of today’s methods, and should reach mass production in 2027, according to DNP and Bits&Chips.

A Dai Nippon Printing nanoimprint template: a small square quartz plate that carries the chip pattern. — The stamp itself: a DNP nanoimprint template, now made with 10 nm lines · Image: DNP.

What nanoimprint can’t do yet

Touching the wafer is NIL’s superpower and its weak spot. A single speck of dust trapped between stamp and wafer can spoil a chip or even damage the mask, Canon’s engineers explain in a company interview. Every layer must also sit on the one below with nanometre precision (engineers call it overlay), and any flaw in the stamp is copied onto every chip, Semiconductor Engineering noted.

Three panels: dust, a speck trapped under the stamp breaking the pattern; alignment, a green layer that must line up with the pink layer below; stamp wear, a stamp with worn teeth pressed on wafer after wafer. — The three hurdles nanoimprint must still clear: dust, alignment and stamp wear (simplified) · Diagram: DIGITAL WOXTER TECHNEWS.

That is why no contract chipmaker has yet committed to NIL for high-volume production, Tom’s Hardware points out. Memory looks like the most likely first home: memory chips repeat the same simple pattern millions of times, which forgives small errors better. Japan’s memory maker Kioxia (formerly Toshiba Memory) has tested Canon’s machines for 3D NAND, the chips inside SSDs, for years, Asia Times reported, but has not announced mass production with it.

The stamp idea is already branching out. In January 2026 Canon unveiled inkjet-based adaptive planarization: an inkjet places just the right amount of liquid where the wafer has dips, then a flat glass plate presses it level, leaving bumps of 5 nm or less across a whole 300 mm wafer in one go. Canon aims to sell the equipment in 2027, according to Canon and MONOist.

A simpler, thriftier EUV: two mirrors instead of six

Instead of replacing EUV, a team at the Okinawa Institute of Science and Technology (OIST) led by Professor Tsumoru Shintake wants to shrink it. Today’s EUV projector bounces light off at least six mirrors, and only about 1% of the light reaches the wafer. Their design uses just two mirrors in a straight line, like a telescope, so more than 10% gets through, OIST says.

The result, on paper: a 20-watt light source and a whole machine using under 100 kW, against more than 1 MW for current systems, as DCD also reports. OIST has filed a patent, but it is unclear how close the design is to a working commercial tool, Tom’s Hardware notes.

Two panels: today's EUV projector bounces the light off at least six mirrors, so about 1% reaches the wafer and the machine uses over 1 megawatt; OIST's design uses two mirrors in a straight line, with over 10% of the light reaching the wafer and under 100 kilowatts, with a 20 watt light source. — Six mirrors or two: OIST's simpler EUV design and its claimed savings · Diagram: DIGITAL WOXTER TECHNEWS.

Side-by-side drawing comparing an industry-standard EUV scanner with many mirrors and OIST's simpler design with two mirrors in a straight line. — Today's EUV optics (left) and OIST's two-mirror design (right) · Image: Tsumoru Shintake (OIST).

The quiet giants: light, chemicals and chiplet printers

Even in factories full of ASML machines, Japanese parts and chemicals are everywhere.

Five Japanese suppliers with arrows into a chip factory: light sources from Gigaphoton, resists from TOK, JSR and Shin-Etsu with about 90% of EUV resist in 2025, templates from DNP with 10 nm lines, Canon's nanoimprint printer with 14 nm lines and Nikon's maskless panel printer for chiplets. Below: EUV scanners come from ASML in the Netherlands. — Japan's place in chip printing: light, chemicals, stamps and printers · Diagram: DIGITAL WOXTER TECHNEWS.

Light sources: Gigaphoton, a Komatsu company in Tochigi, makes excimer lasers, the light sources inside the deep-ultraviolet (DUV) scanners that work alongside EUV in chip factories,, optics.org reported.
Resists: three Japanese firms, Tokyo Ohka Kogyo (TOK), JSR and Shin-Etsu Chemical, supplied about 90% of the world’s EUV resist in 2025, according to QYResearch figures cited by Digital Today. Japanese makers held 72.5% of all photoresist in 2021, SCMP adds.
Metal-oxide resists: for High-NA EUV, resists built from tiny metal-oxide clusters, rather than plastic-like molecules, can soak up more of the scarce EUV light, which helps print sharper, smaller features. In September 2025 JSR’s US unit Inpria and Lam Research agreed to develop them together for High-NA patterning, JSR announced; I-Connect007 covered it too.
Chiplet printers: a chiplet is like building a computer from LEGO bricks instead of one carved block, and the bricks are wired together on big panels. Nikon’s DSP-100 prints those wires with no mask at all,: 1 micrometre lines on panels up to 600 mm square, with first deliveries planned in Nikon’s fiscal year 2026, Nikon says. A faster successor is due in fiscal 2027, TrendForce reports.

Four cards with big numbers: €350 million for one High-NA EUV machine against about €170 million for standard EUV; one-tenth the power for nanoimprint according to Canon and DNP; under 100 kilowatts for OIST's two-mirror EUV design against over 1 megawatt today; 14 nanometre lines from Canon's stamp today and 10 nanometres from DNP's new template. — The big numbers: prices are press estimates, the other figures are the makers' own claims · Diagram: DIGITAL WOXTER TECHNEWS.

More Japanese breakthroughs for next-gen chips

Printing is only one step. Japanese companies are pushing the rest of the chip-making line too:

Checking the masks: an EUV mask must be flawless, and the surest check uses EUV light itself (“actinic” inspection). Lasertec launched the first such machine in 2019 and, in October 2025, a model that inspects three times faster, according to Lasertec and Dempa.
Ice-cold etching: Tokyo Electron’s etcher works at about −70 °C and digs holes 10 micrometres deep in 33 minutes for 3D memory with more than 400 layers, Tom’s Hardware reported; TheElec said shipments would start in 2025.
Taller memory towers: Kioxia began sampling 332-layer 3D flash memory in July 2026, built on two separate wafers (control circuits and memory cells) bonded face to face, a method it calls CBA, say Kioxia and Blocks and Files.
The film inside big chips: Ajinomoto, the food company famous for MSG seasoning, makes the insulating film (ABF) used in more than 95% of CPU and GPU package substrates, and plans to invest at least ¥25 billion by 2030 to make 50% more, TrendForce and TechRadar report.
New factories: TSMC’s Japanese venture JASM runs a fab in Kumamoto and has started building a second one for 6 and 7 nm chips, according to TSMC and TechNode. In Hokkaido, Rapidus processes every wafer one at a time instead of in batches, collecting data to help AI improve its yields, as Rapidus and Tom’s Hardware reported.

Six cards with icons and big numbers: Lasertec, 3 times faster EUV mask checks; Tokyo Electron, etching at −70 °C for 3D memory; Kioxia, 332 layers of 3D flash; Ajinomoto, ABF film in more than 95% of CPU and GPU substrates; TSMC's JASM, a second Kumamoto fab for 6 and 7 nm chips; Rapidus, every wafer processed one by one. — More Japanese breakthroughs across chip-making, from mask checks to packaging film · Diagram: DIGITAL WOXTER TECHNEWS.

Lasertec's ACTIS A200HiT, a large white machine that inspects EUV masks using EUV light. — Lasertec's ACTIS A200HiT checks EUV masks with EUV light, three times faster than its 2019 predecessor · Image: Lasertec.

Where the rest of the world fits

Europe owns the top end through ASML in the Netherlands. South Korea is racing ahead with it: SK hynix assembled the first High-NA EUV machine for mass production at its Icheon fab in September 2025, Tom’s Hardware and TrendForce report, and Samsung has its own. Taiwan‘s TSMC, the biggest contract chipmaker, builds its leading chips with EUV, and JSR is building its first photoresist plant in Taiwan, Taiwan News and Tom’s Hardware report.

China, which cannot buy EUV machines under export rules, is chasing nanoimprint too: local firm Prinano delivered its first step-and-repeat NIL tool in 2025, Notebookcheck reported. And Japan’s own leading-edge hope, Rapidus and its 2 nm factory in Hokkaido, prints with ASML’s EUV. For Latin America, Spain and the rest of the EU, DNP’s pitch is the interesting part: cheaper patterning for chipmakers without EUV.

What happens next

2026-2027: Nikon’s first DSP-100 deliveries for chiplet packaging (its fiscal year ends in March 2027).
2027: DNP’s mass production of 10 nm nanoimprint templates and Canon’s first planarization machines, if plans hold.
The big one: a memory or logic maker announcing nanoimprint for real mass production. Kioxia is the name to watch.
Okinawa: any prototype or industry partner for OIST’s two-mirror EUV would be the first sign it can leave the lab.

EUV is not going anywhere soon. But the next chip in your phone may well carry a Japanese stamp, a Japanese resist or a Japanese laser somewhere inside.